1. Field of the Invention
The invention relates to disk array controllers, and more specifically to disk array controllers having bus mastering capabilities and local processing capabilities.
2. Description of the Prior Art
Personal computers are becoming even more powerful. They are reaching levels where they are displacing minicomputers and even mainframe computers. In this downsizing environment, a local area network (LAN) is the basic unit. ALAN typically has one or more file servers and a large number of individual workstations. In most cases the file servers are used as storage hubs for the various files, with copies of the files being transferred to the workstations on demand and updated files being returned for storage. As a result, the disk subsystem used in the file server reflects directly on the performance of the LAN.
This performance requirement has lead to great advances in both disk drives themselves and the architecture of the disk subsystem. Disk storage sizes have increased, access times have decreased and data transfer rates have increased. However, as more downsizing occurs and larger numbers of workstations are connected to the LAN, there is still continual pressure on improving disk subsystem performance. Disk drives used with mainframes offer high performance, but are very large and very expensive. Smaller, much cheaper drives are preferred. However, as more disk drives are used, the failure rate increases dramatically. Several solutions to the failure problem are available. The simplest is to provide complete redundant disk drives. This is referred to as mirroring. One problem with mirroring is storage efficiency. One half of the available capacity is used for redundancy. This is a relatively high penalty. As a remedy to this drawback, in an article entitled "A Case for Redundant Arrays of Inexpensive Disks (RAID)", ACM Sigmod Conference, June 1988, D. Patterson et al. proposed various Redundant Array of Inexpensive Disk (RAID) architectures. Two levels are of particular interest, namely RAID 4 and RAID 5. Both use data striping, where logical data is striped across the array of disks, and parity protection. In parity protection, the data values of each disk drive sector forming a stripe are XOR'd to develop a parity sector. This is written to a position in the stripe. In RAID 4 all parity information is contained on one disk drive, while in RAID 5 the parity information is spread across the drives in a skewed or diagonal fashion. A RAID 5 architecture is slightly more complicated to develop, but assuming the overheads can be reduced, offers an improved overall performance as one drive does not form a bottleneck because of parity data storage or recovery.
Given the processing and control requirements of RAID 4 and RAID 5 implementations, preferably a dedicated processor is used to control operations. Use of the host system processor would dramatically reduce overall performance. One solution to the development of a RAID 4 system is disclosed in U.S. patent application Ser. No. 431,735, entitled "Disk Array Controller With Parity Capabilities," which is hereby incorporated by reference, where a local processor controls a specialized DMA controller arrangement. The DMA controllers perform the main data transfer tasks, with the local processor only performing command interpretation and control functions.
While that design provided great improvements over host computer control, several areas for improvement were available. One major area for improvement was the actual transfer of data between the controller and the host system. The Intel Corp. 82355 or BMIC chip was used as the bus mastering device on the EISA bus. This chip had the problem that it was a master device on the local internal bus. Thus operations were difficult as the local processor had to program the BMIC before transfers were performed. This greatly increased overhead for the local processor and slowed down operations. Further, the internal bus was basically not expandable, so the design was limited in that respect. This design of the BMIC limited the capabilities of the DMA controller to just relatively simple DMA functions. This resulted in even further overhead increases for the local processor as each and every transfer operation of the DMA controllers had to be fully setup by the local processor. This setup required numerous input/output operations, which was a portion of the overhead increase.
Therefore a structure allowing more flexible operations on the local bus allowing transfers to the host system without local processor operations and less control requirements for many transfers is desirable to reduce local processor overhead to allow improved performance of a disk array controller.